1. Field of the Invention
The present invention relates to a method of constructing the testing procedures of an analog circuit by applying the fault classification tables of this analog circuit. The constructing method classifies the fault classification tables to establish a decision tree. Entropy definitions are defined and the decision tree can be established by following the rule of decreasing the entropy values. A search procedure of the decision tree can be performed as to find the failure mode next time when the analog circuit is detected.
The invention is related to another U.S. patent application Ser. No. 08/906,087 entitled "Method for Constructing Fault Classification Tables of Analog Circuits" assigned to same assignee as the present application and incorporated herein by reference in its entirety.
2. Description of the Prior Art
As electric technologies go on getting progresses, there are kinds of electric products coming into human's life. However, a great deal of control circuits such as digital and analog circuits are needed to control the operations of the electric products. Everyone should agree that the control circuits can be treated as the souls of the electric products. Therefore, the control circuits must pass many testing procedures before obtaining a required design.
An early testing scheme needs to actually implement the designed circuits after completing the circuit diagram, and perform the testing procedures to the actual circuit for detecting whether the designed circuit achieves the design purpose. When the detecting result is out of expect, the circuit designer must modify the circuit diagram and implement the modified circuit for testing again. The above testing procedure keeps going until the modified circuit achieves the designed requirement. However, this testing procedure wastes many circuit materials, and needs professional circuit engineers to perform this detecting routine. Clearly, it is not an efficient testing scheme.
In order to overcome the disadvantage of the conventional scheme, tools derived from computer aided engineering (CAE) is growing up. The CAE is a computer program established in a workstation or a personal computer. A circuit designer uses graphic icon to build a circuit diagram, and then performs a simulation procedure to the designed circuit by using a simulation package. The simulation package is composed of software modules, which compiles the designed circuit diagram and converts it into circuit modules with wires as connections. The simulation procedure inputs a pulse into the circuit modules, and then calculates the voltages (or current) estimations at each node of the circuit modules. Output waveform generated by the simulation procedure is displayed to the designer when the simulation procedure terminates. The designer can modify the circuit diagram and perform the simulation procedure until the designed circuit achieves his requirement. Of course, the CAE can significantly degrade the time for designing a circuit, and furthermore, the CAE also can save many circuit materials that are unnecessarily wasted.
Computer aided testing (CAT) is a tool extending the applications of the CAE and simulation to the field of circuit testing. The CAT tools apply failure modes that insert the fault models but the normal models in parts of the circuit components (for example, a fault model simulates the characteristic of a diode acts when punch through appears), and then starts the simulation procedure to record the output waveform as a fault dictionary. Next time when the circuit is testing, the testing result can be compared with the fault dictionary to find the defect components.
In the present days, only the digital CAT tools have been completely developed. However, the characteristics of the analog circuit are quite different with the digital, and thus the analog CAT tools are deficient now. In the prior skills, such as the article "Simulation-based testability analysis and fault diagnosis" disclosed by Sujoy et al. in IEEE Transaction on Autotestcon on September 1996, only a simple classification scheme is suggested to the test points of the analog circuit.
Unfortunately, each the measured value is not fixed but varies in a tolerance range that is caused by the environment around the circuit and by the defects of the circuit components. For example, the measured value 10 may vary in the tolerance range (8.5, 11.5). However, a larger tolerance range will affect decisions to the measured values. Furthermore, a fault decision may be done while there are many test points are applied, which will bring troubles to the fault dictionary generated by Sujoy et al. What is clearly needed is reliable testing tools for overcoming the disadvantages of the conventional skills.